Integrated circuits are generally mass produced by semiconductor design companies. In designing the integrated circuit, engineers at a design company use computer-aided tools to develop an electronic mask set, which represents different layers of the integrated circuit. This electronic mask set is then used to generate a set of physical masks, which are in turn used to fashion features on different layers of a physical integrated circuit during manufacturing.
As design companies strive to deliver more powerful integrated circuits at lower cost points, the design companies continuously try to “pack” more transistors into a given area on each integrated circuit. This is often achieved by shrinking feature sizes of the devices, which generally results in integrated circuits that exhibit improved speed and power characteristics. Although shrinking is often advantageous from a performance perspective, it is often difficult from a manufacturing perspective to continue to shrink device features from one technology node to the next.
In particular, it is becoming especially difficult to pattern interconnect lines, which tend to be very closely spaced. Thus, during photolithography, the close proximity of the interconnect lines gives rise to a lack of contrast between exposed and unexposed photoresist regions which correspond to the interconnect lines. This lack of contrast makes it difficult, if not impossible, to form interconnect lines in extremely close proximity using traditional techniques. Accordingly, new methods and systems for patterning layers of integrated circuits are needed.